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IEEE-696

1     (Component side)      50
==============================
100     (Solder side)       51

Pin Name Type Dir Description
1 +8 V Power --> +8 Volts
2 +16 V Power --> +16 Volts
3 XRDY Fr panel --> External Ready To Processor
4 /VI0 Control <-- Vector Interrupt Line 0
5 /VI1 Control <-- Vector Interrupt Line 1
6 /VI2 Control <-- Vector Interrupt Line 2
7 /VI3 Control <-- Vector Interrupt Line 3
8 /VI4 Control <-- Vector Interrupt Line 4
9 /VI5 Control <-- Vector Interrupt Line 5
10 /VI6 Control <-- Vector Interrupt Line 6
11 /VI7 Control <-- Vector Interrupt Line 7
12 /NMI Control <-- Non-maskable Interrupt
13 /PWRFAIL <-> Power fail bus signal
14 /TMA3 --> Temporary master priority bit 3
15 A18 Address --> Extended Address Bit 18
16 A16 Address --> Extended Address Bit 16
17 A17 Address --> Extended Address Bit 17
18 /SDSB Control <-- Disable Processor Status Lines
19 /CDSB Control <-- Disable Processor Control Lines
20 GND Power --- Ground
21
22 /ADSB Control --> Disable Processor Address Lines
23 /DODSB Control --> Disable Processor Data Out Lines (DO7-0 for 8-bit transfer, ED7-0 & OD7-0 for 16-bit transfer.)
24 phi2,phi0 Clock --> Primary Processor Clock Line
25 /PSTVAL Clock --> Status Valid Strobe
26 PHLDA Control --> Processor In Hold Condition
27 rsvd reserved
28 rsvd reserved
29 A5 Address --> Address Line 5
30 A4 Address --> Address Line 4
31 A3 Address --> Address Line 3
32 A15 Address --> Address Line 15
33 A12 Address --> Address Line 12
34 A9 Address --> Address Line 9
35 DO1 D1 Data --> <-> Data Output Line 1 / Bidirectional Data Bit 1
36 DO0 D0 Data --> <-> Data Output Line 0 / Bidirectional Data Bit 0
37 A10 Address --> Address Line 10
38 DO4 D4 Data --> <-> Data Output Line 4 / Bidirectional Data Bit 4
39 DO5 D5 Data --> <-> Data Output Line 5 / Bidirectional Data Bit 5
40 DO6 D6 Data --> <-> Data Output Line 6 / Bidirectional Data Bit 6
41 DI2 D10 Data <-- <-> Data Input Line 2 / Bidirectional Data Bit 10
42 DI3 D11 Data <-- <-> Data Input Line 3 / Bidirectional Data Bit 11
43 DI7 D15 Data <-- <-> Data Input Line 7 / Bidirectional Data Bit 15
44 SM1 State --> Processor Instruction Fetch Signal
45 SOUT State --> Processor I/O Write Signal
46 SINP State --> Processor I/O Read Signal
47 SMEMR State --> Processor Memory Read Signal
48 SHLTA State --> Processor Halted Signal
49 CLOCK Clock --> 2MHz Clock Signal
50 GND Power --- Logical And Power Ground
51 +8V Power --> +8 Volts
52 -16V Power --> -18 Volts
53 GND Power --- Ground
54 /S CLR Fr panel --> Reset to Bus slaves
55 /DMA0 Control --> Temporary Master Priority Bit 0
56 /DMA1 Control --> Temporary Master Priority Bit 1
57 /DMA2 Control --> Temporary Master Priority Bit 2
58 /SXTRQ Control --> Front Panel Ready (Altair)
59 A19 Address --> Extended Address Bit 19
60 /SIXTN Fr panel ??? See Note 1
61 A20 Address --> Extended Address Bit 20
62 A21 Address --> Extended Address Bit 21
63 A22 Address --> Extended Address Bit 22
64 A23 Address --> Extended Address Bit 23
65
66
67 /PHANTOM <-> Disables normal slave devices and enables phantom slaves (primarily used for bootstrapping systems without hardware front panels).
68 MWRT Ctrl/frp --> Memory Write From Processor Or Front Panel
69 rsvd reserved
70 GND Fr panel --- Ground
71 rsvd reserved
72 RDY Control <-- Controls Run/Wait State Of Processor
73 /INT Control <-- Request For Interrupt To Processor
74 /HOLD Control <-- Request For Hold To Processor
75 /RESET Control <-> Forces Processor To Reset State
76 pSYNC Control --> Marks Beginning Of Each Processor Cycle
77 /pWR Control --> Active When Processor Writes (I/O Or Memory)
78 pDBIN Control --> Active When Processor Reads (I/O Or Memory)
79 A0 Address --> Address Line 0
80 A1 Address --> Address Line 1
81 A2 Address --> Address Line 2
82 A6 Address --> Address Line 6
83 A7 Address --> Address Line 7
84 A8 Address --> Address Line 8
85 A13 Address --> Address Line 13
86 A14 Address --> Address Line 14
87 A11 Address --> Address Line 11
88 DO2 D2 Data --> <-> Data Output Line 2 / Bidirectional Data Bit 2
89 DO3 D3 Data --> <-> Data Output Line 3 / Bidirectional Data Bit 3
90 DO7 D7 Data --> <-> Data Output Line 7 / Bidirectional Data Bit 7
91 DI4 D12 Data <-- <-> Data Input Line 4 / Bidirectional Data Bit 12
92 DI5 D13 Data <-- <-> Data Input Line 5 / Bidirectional Data Bit 13
93 DI6 D14 Data <-- <-> Data Input Line 6 / Bidirectional Data Bit 14
94 DI1 D9 Data <-- <-> Data Input Line 1 / Bidirectional Data Bit 9
95 DI0 D8 Data <-- <-> Data Input Line 0 / Bidirectional Data Bit 8
96 SINTA Control --> Acknowledge Signal For Pint Request
97 /SWO Control --> Processor In Write Status
98 /ERROR Control --> Error condition during present Bus Cycle
99 /POC Ft panel <-> Power-On Clear Signal
100 GND Power --- Power And Signal Ground

Note: Direction is CPU/Frontpanel relative cards.

Power

Name Minimum Maximum
(Power on)
Maximum
(Average)
+8V +7V +25V +11V
+16V +14.5V +35V +21.5V
-16V -14.5V -35V -21.5V

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