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IMSAI 8080 bus

1     (Component side)      50
==============================
100     (Solder side)       51

Pin Name Type Dir Description
1 +8 V Power --> +8 Volts
2 +18 V Power --> +18 Volts
3 XRDY Fr panel --> External Ready To Processor
4 VI 0 Control <-- Vector Interrupt Line 0
5 VI 1 Control <-- Vector Interrupt Line 1
6 VI 2 Control <-- Vector Interrupt Line 2
7 VI 3 Control <-- Vector Interrupt Line 3
8 VI 4 Control <-- Vector Interrupt Line 4
9 VI 5 Control <-- Vector Interrupt Line 5
10 VI 6 Control <-- Vector Interrupt Line 6
11 VI 7 Control <-- Vector Interrupt Line 7
12
13
14
15
16
17
18 /STADSB Control <-- Disable Processor Status Lines
19 /CCDSB Control <-- Disable Processor Control Lines
20 T5 ? ? T5?
21 SS Fr panel --> Single Step Processor
22 /ADDDSB Control <-- Disable Processor Address Lines
23 /DODSB Control <-- Disable Processor Data Out Lines
24 phi2 Clock --> Primary Processor Clock Line
25 phi1 Clock --> “Inversion” Of Phase 2 Processor Clock Line
26 PHLDA Control --> Processor In Hold Condition
27 PWAIT Control --> Processor In Wait Condition
28 PINTE Control --> Processor Permits Interrupts When Active
29 A5 Address --> Address Line 5
30 A4 Address --> Address Line 4
31 A3 Address --> Address Line 3
32 A15 Address --> Address Line 15
33 A12 Address --> Address Line 12
34 A9 Address --> Address Line 9
35 DO1 Data --> Data Output Line 1
36 DO0 Data --> Data Output Line 0
37 A10 Address --> Address Line 10
38 DO4 Data --> Data Output Line 4
39 DO5 Data --> Data Output Line 5
40 DO6 Data --> Data Output Line 6
41 DI2 Data <-- Data Input Line 2
42 DI3 Data <-- Data Input Line 3
43 DI7 Data <-- Data Input Line 7
44 SM1 State --> Processor Instruction Fetch Signal
45 SOUT State --> Processor I/O Write Signal
46 SINP State --> Processor I/O Read Signal
47 SMEMR State --> Processor Memory Read Signal
48 SHLTA State --> Processor Halted Signal
49 /CLOCK Clock --> 2Mhz Clock Signal
50 GND Power --- Logical And Power Ground
51 +8 V Power --> +8 Volts
52 -18 V Power --> -18 Volts
53 /SSW DSBL Fr panel --> Sense Switch Disable (Of Data Inputs)
54 /EXTCLR Fr panel --> Clear (Reset) I/O Devices On Bus
55
56
57
58
59
60
61
62
63
64
65
66
67 /PHANT ? ? Phantom?
68 MWRT Ctrl/frp --> Memory Write From Processor Or Front Panel
69
70 GND Power --- Ground
71 RUN Fr panel --> Stops Processor
72 PRDY Control <-- Controls Run/Wait State Of Processor
73 /PINT Control <-- Request For Interrupt To Processor
74 /PHOLD Control <-- Request For Hold To Processor
75 /PRESET Control <-- Forces Processor To Reset State
76 PSYNC Control --> Marks Beginning Of Each Processor Cycle
77 /PWR Control --> Active When Processor Writes (I/O Or Memory)
78 PDBIN Control --> Active When Processor Reads (I/O Or Memory)
79 A0 Address --> Address Line 0
80 A1 Address --> Address Line 1
81 A2 Address --> Address Line 2
82 A6 Address --> Address Line 6
83 A7 Address --> Address Line 7
84 A8 Address --> Address Line 8
85 A13 Address --> Address Line 13
86 A14 Address --> Address Line 14
87 A11 Address --> Address Line 11
88 DO2 Data --> Data Output Line 2
89 DO3 Data --> Data Output Line 3
90 DO7 Data --> Data Output Line 7
91 DI4 Data <-- Data Input Line 4
92 DI5 Data <-- Data Input Line 5
93 DI6 Data <-- Data Input Line 6
94 DI1 Data <-- Data Input Line 1
95 DI0 Data <-- Data Input Line 0
96 SINTA Control --> Acknowledge Signal For Pint Request
97 /SWO Control --> Processor In Write Status
98 SSTACK Control --> Processor In Stack Read/Write Status
99 /POC Ft panel --> Power-On Clear Signal
100 GND Power --- Power And Signal Ground

Note: Direction is CPU/Frontpanel relative cards.

See also

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